Shift registers are indispensable circuits for a semiconductor memory device having serial input/output. The semiconductor memory device senses data at the time of readout, and outputs data serially by storing the data in the shift registers. Moreover, the semiconductor memory device performs writing serially by storing write data in the shift registers at the time of writing. Japanese Patent Application Publication No. 2004-64557 discloses such shift registers.
The shift registers are separated from each other. The shift registers shift data in the same direction. Each of the shift registers is connected to the adjacent one of the shift registers. A line to connect the separate shift registers is longer than a line to connect flip-flops provided inside each of the shift registers. Accordingly, the shift registers have large resistance or large parasitic capacitance so that the shift registers operate with low maximum operation frequency. As a result, the shift registers have a problem of being incapable of performing high-speed serial input/output access.